1. Field of the Invention
The present invention relates to speeding-up and functional improvement of display apparatus.
2. Description of the Prior Art
The speeding-up of display apparatus is generally required in the fields of document-and-image treating systems such as OA systems and graphic treating systems such as CAD/CAM systems. Particularly, in the CAD/CAM fields executing high-speed simulation and the like, various efforts have been made for the speeding-up purposes. Of the conventional speeding-up techniques, the process-distributing method is widely used as one general speeding-up technique, and a study and realizable example of a distributed type graphic display are disclosed in "A transputer based distributed graphic display" (TRANSPUTER TECHNICAL NOTES, INMOS Limited, Prentice Hall, 1989, p170-204). Moreover, in the recent high-speed graphic work station and the like, the speeding-up of the drawing operation is made by dividing a frame memory.
Although in these conventional display apparatus the speeding-up can be realized due to the distributing technique, there is a problem, however, in that its hardware has a fixed arrangement which is not necessarily optimal for application to the CAD/CAM requiring various expressions. As the graphic applications in the CAD/CAM field, there are complicated three-dimensionally shaped shading display and high-speed two-dimensionally imaged animation display, for example. The former bears a heavy calculation load for the pre-processing such as coordinate transformation and calculation of surface brightness and on the other hand the latter bears a heavy load for the output-side processing such as image transfer on a frame memory. In order to try to make the speeding-up of both the displays in the graphic work station or the like, at the previous stage a plurality of calculation processors are coupled through pipe lines to each other and at the output stage a frame memory is divided into regions each of which is coupled to a writing processor. Thus, the system is equipped with a number of processors as illustrated in FIG. 9 so as to become large in scale and high in cost. In FIG. 9, EP represents a processor acting as a calculation means, MEM designates a memory, DP denotes a processor functioning as a display data writing means, and FMEM depicts a frame memory.
In addition, in the case of operating the above-described applications, a problem arises in terms of the processor efficiency due to deviation of the processing load.